There are two types of timing controls in Verilog - delay and event expressions. The delay control is just a way of adding a delay between the time the simulator encounters the statement and when it actually executes it. The event expression allows the statement to be delayed until the occurrence of some simulation event which can be a change of value on a net or variable (implicit event) or an explicitly named event that is triggered in another procedure.
Simulation time can be advanced by one of the following methods.
Verilog code updown counter with load; verilog code for Moore 101; verilog code for FIFO; verilog code for johnsons counter; Verilog code for Linear feedback shift register; verilog code for Mealy 101 detector; verilog code for rotate bits; verilog code for Serial ALU; verilog code of traffic light; verilog code for different FLIP-FLOPS. Sequential Circuit Design with Verilog ECE 152A – Winter 2012 February 15, 2012 ECE 152A -Digital Design Principles 2 Reading Assignment Brown and Vranesic 6 Combinational – Circuit Building Blocks 6.6 Verilog for Combinational Circuits 6.6.1 The Conditional Operator 6.6.2 The If-Else Statement 6.6.3 The Case Statement.
Gates and nets that have been modeled to have internal delays also advance simulation time.
Delay Control
If the delay expression evaluates to an unknown or high-impedance value it will be interpreted as zero delay. If it evaluates to a negative value, it will be interpreted as a 2's complement unsigned integer of hte same size as a time variable.
Note that the precision of timescale is in 1ps and hence
Simulation Log$realtime
is required to display the precision value for the statement with a delay expression (a+b)*10ps.Click to try this example in a simulator!
Event Control
Value changes on nets and variables can be used as a synchronization event to trigger execution other procedural statements and is an implicit event. The event can also be based on the direction of change like towards 0 which makes it a
negedge
and a change towards 1 makes it a posedge
.- A
negedge
is when there is a transition from 1 to X, Z or 0 and from X or Z to 0 - A
posedge
is when there is a transition from 0 to X, Z or 1 and from X or Z to 1
A transition from the same state to the same state is not considered as an edge. An edge event like posedge or negedge can be detected only on the LSB of a vector signal or variable. If an expression evaluates to the same result it cannot be considered as an event.
Simulation LogNamed Events
The keyword
event
can be used to declare a named event which can be triggered explicitly. An event
cannot hold any data, has no time duration and can be made to occur at any particular time. A named event is triggered by the ->
operator by prefixing it before the named event handle. A named event can be waited upon by using the @
operator described above.Named events can be used to synchronize two or more concurrently running processes. For example, the
Simulation Logalways
block and the second initial
block are synchronized by a_event. Events can be declared as arrays like in the case of b_event which is an array of size 5 and the index 3 is used for trigger and wait purpose.Event or operator
The
or
operator can be used to wait on until any one of the listed events is triggered in an expression. The comma ,
can also be used instead of the or
operator.Simulation Log
Implicit Event Expression List
The sensitivity list or the event expression list is often a common cause for a lot of functional errors in the RTL. This is because the user may forget to update the sensitivity list after introducing a new signal in the procedural block.
Simulation LogIf the user decides to add new signal e and capture the inverse into z, special care must be taken to add e also into the sensitivity list.
Simulation LogVerilog now allows the sensitivity list to be replaced by
Simulation Log*
which is a convenient shorthand that eliminates these problems by adding all nets and variables that are read by the statemnt like shown below.Level Sensitive Event Control
Execution of a procedural statement can also be delayed until a condition becomes true and can be accomplished with the
wait
keyword and is a level-sensitive control.The wait statement shall evaluate a condition and if it is false, the procedural statements following it shall remain blocked until the condition becomes true.
Simulation LogClick to try this example in a simulator!
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//author: shvlad |
//email: [email protected] |
// synopsys translate_off |
`timescale1 ns /100 ps |
// synopsys translate_on |
//`default_nettype none |
modulecam_wrp |
( |
inputwire rst_n, |
inputwire [7:0] data_cam, |
inputwire HREF_cam, |
inputwire PCLK_cam, |
inputwire ctrl_busy, |
outputwire [15:0] input_fifo_to_sdram, |
outputreg [23:0] addr_sdram, |
outputreg wr_enable |
); |
reg [15: 0] data2fifo; |
reg sh_HREF_cam; |
reg wr_fifo; |
wire [9:0] output_rdusedw; |
always @( posedge PCLK_cam ornegedge rst_n ) |
if ( ! rst_n ) |
begin |
sh_HREF_cam <=1'h0; |
end |
else |
begin |
sh_HREF_cam <= HREF_cam; |
end |
always @( posedge PCLK_cam ornegedge rst_n ) |
if ( !rst_n ) |
data2fifo <=16'h0; |
else |
if ( wr_fifo ) |
data2fifo[7:0] <= data_cam; |
else |
data2fifo[15:8] <= data_cam; |
always @( posedge PCLK_cam ornegedge rst_n ) |
if ( !rst_n ) |
wr_fifo <=1'h0; |
else |
if ( HREF_cam ) |
wr_fifo <=!wr_fifo; |
else |
wr_fifo <=1'h0; |
reg [8:0] sh_write; |
initial sh_write=9'd0; |
reg wr_enable_fifo=1'b0; |
always @(posedge ctrl_busy ornegedge rst_n) |
begin |
if (!rst_n) |
begin |
sh_write=9'd0; |
wr_enable<=1'b1; |
wr_enable_fifo=1'b1; |
addr_sdram=24'd0; |
end |
else |
begin |
if ((output_rdusedw>600)&&(sh_write9'd0)) wr_enable<=1'b1; |
if ((output_rdusedw<600)&&(sh_write9'd320)) wr_enable<=1'b0; |
if (wr_enable) |
begin |
if (sh_write!=0) |
begin |
if (addr_sdram<24'd76799) addr_sdram=addr_sdram+1'b1; |
else addr_sdram=24'd0; |
end |
if (sh_write<9'd320) sh_write=sh_write+1'b1; |
else sh_write=9'd0; |
end |
end |
end |
fifo_1024x16input_fifo |
( |
.aclr ( !rst_n ), |
.data ( data2fifo ), |
.rdclk ( ctrl_busy ), |
.rdreq ( wr_enable && (sh_write<=9'd319) ), |
.wrclk ( PCLK_cam ), |
.wrreq ( !wr_fifo && sh_HREF_cam ), |
.q ( input_fifo_to_sdram ), |
.rdempty ( ), |
.rdusedw ( output_rdusedw ), |
.wrfull ( ), |
.wrusedw ( ) |
); |
endmodule |
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